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Preliminary Technical Data
FEATURES
Ultra low power 3.3 V, 90 uA Response time 10 ms Adaptive environmental compensation Two independent capacitance input channels Sensor capacitance (CSENS) 0 up to 14 pF Sensitivity to 0.8 fF EMC tested Two modes of operation: Standalone with fixed settings Interfaced to a uC for user-defined settings Two proximity detection output flags 2-wire serial interface (I2C(R)-compatible) Operating temperature: -40C to +125C 10-lead uSOIC package
Ultra Low Power, 2 Channel, Capacitance Converter for Proximity Sensing AD7150
GENERAL DESCRIPTION
The AD7150 delivers a complete signal processing solution for capacitive proximity sensors, featuring an ultra low power converter with fast response time. The AD7150 uses Analog Devices' capacitance to digital converter (CDC) technology, which combines features important for interfacing to real sensors, such as a high input sensitivity and a high tolerance of both input parasitic ground capacitance and leakage current. The integrated adaptive threshold algorithm compensates for any variations in the sensor capacitance due to environmental factors like humidity and temperature, or changes in the dielectric material over time. By default, the AD7150 operates in standalone mode using the fixed power up settings and indicates detection on two digital outputs. Alternatively, the AD7150 can be interfaced to a uC via I2C interface, the internal registers can be programmed with user-defined settings and the data and status can be read from the part. The AD7150 operates from a 3.3 V power supply. It is specified over the temperature range of -40C to +125C.
APPLICATIONS
Proximity sensing Contact-less switching Position detection Level detection
FUNCTIONAL BLOCK DIAGRAM
VDD CIN1 - CDC EXC1 CIN2 MUX DIGITAL FILTER SERIAL INTERFACE SCL SDA
CSENS1
AD7150
THRESHOLD
OUT1
CSENS2
EXCITATION EXC2
THRESHOLD
OUT2
GND
Figure 1.
Rev. PrD, 8. November 2006
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 (c) 2006 Analog Devices, Inc. All rights reserved.
AD7150
Preliminary Technical Data
TABLE OF CONTENTS
Preliminary Specifications............................................................... 3 Timing Specifications....................................................................... 4 Absolute Maximum Ratings............................................................ 5 Pin Configurations and Function Descriptions ........................... 6 Typical Performance Characteristics ............................................. 7 Architecture and Main Features ..................................................... 8 Overview........................................................................................ 8 Capacitance to Digital Converter............................................... 8 CAPDAC ....................................................................................... 8 Comparator and Threshold Modes............................................ 9 Adaptive Threshold...................................................................... 9 Data Average ................................................................................. 9 Sensitivity .................................................................................... 10 Hysteresis..................................................................................... 10 Timeout........................................................................................ 10 Auto CAPDAC adjustment ....................................................... 10 Power Down Timer .................................................................... 10 Register Descriptions ..................................................................... 11 Status Register ............................................................................. 12 Data Registers ............................................................................. 12 Average Registers........................................................................ 12 Fixed Threshold Registers ......................................................... 12 Sensitivity Registers ................................................................... 13 Timeout Registers....................................................................... 13 Setup Registers............................................................................ 14 Configuration Register .............................................................. 15 Power Down Timer Register .................................................... 16 Cap DAC B Registers ................................................................. 16 Serial Number Registers ............................................................ 16 Chip ID Registers ....................................................................... 16 Serial Interface ................................................................................ 17 Read Operation .......................................................................... 17 Write Operation.......................................................................... 17 AD7150 Reset ............................................................................. 18 General Call ................................................................................ 18 Hardware Design Considerations ................................................ 19 Overview ..................................................................................... 19 Parasitic Capacitance to Ground.............................................. 19 Parasitic Resistance To Ground................................................ 19 Parasitic Parallel Resistance ...................................................... 19 Parasitic Serial Resistance ......................................................... 20 Input Overvoltage Protection ................................................... 20 Input EMC Protection ............................................................... 20 Application Examples ................................................................ 21
REVISION HISTORY Pre-Release Preliminary Datasheet
Rev. PrD | Page 2 of 24
Preliminary Technical Data
PRELIMINARY SPECIFICATIONS
VDD = 3.0 V to 3.6 V; GND = 0 V; -40C to +125C, unless otherwise noted. Table 1.
Parameter CAPACITIVE INPUT Capacitive Input Ranges Min Typ 4 2 1 0.5 2.0 1.6 1.4 0.8 100 10 TBD TBD 10 160 25 75 0.4 VDD - 0.6 Max Unit pF1 pF pF pF fF1 fF fF fF pF ms fF/V dB pF fF % of CIN Range V V ISINK = 8 mA ISOURCE = 8 mA
AD7150
Test Conditions/Comments
Resolution
4 pF Range 2 pF Range 1 pF Range 0.5 pF Range
Allowed Capacitance to GND Response time Power Supply Rejection Channel-to-Channel Isolation CAPDAC 2 Full Range Resolution AutoDAC Increment / Decrement LOGIC OUTPUTS (OUT1, OUT2) VOL Output Low Voltage VOH Output High Voltage SERIAL INTERFACE LOGIC INPUTS (SCL, SDA) VIH Input High Voltage VIL Input Low Voltage Hysteresis Input Leakage Current (SCL) OPEN-DRAIN OUTPUT (SDA) VOL Output Low Voltage IOH Output High Leakage Current POWER REQUIREMENTS VDD-to-GND Voltage IDD Current 3 IDD Current Power-Down Mode 3
2.1 0.8 150 0.1 1 0.4 0.1 3.0 90 1 1 3.6 100 180 TBD TBD
V V mV A V A V A A A uA ISINK = -6.0 mA VOUT = VDD VDD = 3.3 V, nominal -40C to +85C -40C to +125C -40C to +85C -40C to +125C
1 2
Capacitance units: 1 pF = 10-12 F; 1 fF = 10-15 F. The CAPDAC can be used to shift (offset) the input range. The total capacitance of the sensor can be therefore up to sum of the max CAPDAC value and the input range. With the auto CAPDAC feature, the CAPDAC is adjusted automatically when the CDC input value is lower than 25% or higher than 75% of the CDC input range. 3 Digital inputs equal to VDD or GND
Rev. PrD| Page 3 of 24
AD7150 TIMING SPECIFICATIONS
Preliminary Technical Data
VDD = 3.0 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; -40C to +125C, unless otherwise noted. Table 2.
Parameter SERIAL INTERFACE1, 2 SCL Frequency SCL High Pulse Width, tHIGH SCL Low Pulse Width, tLOW SCL, SDA Rise Time, tR SCL, SDA Fall Time, tF Hold Time (Start Condition), tHD;STA Set-Up Time (Start Condition), tSU;STA Data Set-Up Time, tSU;DAT Set-Up Time (Stop Condition), tSU;STO Data Hold Time, tHD;DAT (Master) Bus-Free Time (Between Stop and Start Condition, tBUF)
1 2
Min 0 0.6 1.3
Typ
Max 400
Unit kHz s s s s s s s s s s
Test Conditions/Comments See Figure 2
0.3 0.3 0.6 0.6 0.1 0.6 0 1.3
After this period, the first clock is generated Relevant for repeated start condition
Sample tested during initial release to ensure compliance. All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Output load = 10 pF.
tLOW
SCL
tR
tF
tHD:STA
tHD:STA
SDA
tHD:DAT
tHIGH tSU:DAT
tSU:STA
tSU:STO
tBUF
P S S P
Figure 2. Serial Interface Timing Diagram
Rev. PrD | Page 4 of 24
05468-003
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter Positive Supply Voltage VDD to GND Voltage on any Input or Output to GND ESD Rating (ESD Association Human Body Model, S5.1) Operating Temperature Range Storage Temperature Range Junction Temperature uSOIC Package JA, (Thermal Impedance-to-Air) uSOIC Package JC, (Thermal Impedance-to-Case) Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature Rating
AD7150
-0.3 V to + 3.9 V
-0.3 V to VDD + 0.3 V TBD V -40C to +125C -65C to +150C 150C 206C/W 44 C/W 300C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrD| Page 5 of 24
AD7150 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Preliminary Technical Data
GND VDD CIN2 CIN1 EXC2
1 2 3 4 5
10
SDA SCL OUT2 OUT1 EXC1
AD7150
TOP VIEW (Not to Scale)
9 8 7 6
Figure 3. AD7150 Pin Configuration(10-Lead MSOP)
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic GND VDD CIN2 CIN1 EXC2 EXC1 OUT1 OUT2 SCL SDA Description Ground Pin. Power Supply Voltage. This pin should be decoupled to GND, using a low impedance capacitor, for example 0.1 F X7R multilayer ceramic. CDC Capacitive Input Channel 2. The measured capacitance (sensor) is connected between the EXC2 pin and CIN2 pin. If not used, this pin can be left open circuit or connected to GND. CDC Capacitive Input Channel 1. The measured capacitance (sensor) is connected between the EXC1 pin and CIN1 pin. If not used, this pin can be left open circuit or connected to GND. CDC Excitation Output. The measured capacitance is connected between the EXC2 pin and CIN2 pin. If not used, this pin should be left as an open circuit. CDC Excitation Output. The measured capacitance is connected between the EXC1 pin and CIN1 pin. If not used, this pin should be left as an open circuit. Logic output. High level on this output indicates proximity detected on capacitive input 1. Logic output. High level on this output indicates proximity detected on capacitive input 2. Serial Interface Clock Input. Connects to the master clock line. Requires a pull-up resistor if not provided elsewhere in the system. Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not provided elsewhere in the system.
Rev. PrD | Page 6 of 24
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
AD7150
Figure 4.
Figure 7.
Figure 5.
Figure 8.
Figure 6.
Figure 9.
Rev. PrD| Page 7 of 24
AD7150 ARCHITECTURE AND MAIN FEATURES
+3.3V VDD CLOCK GENERATOR PWR DOWN TIMER CIN1
Preliminary Technical Data
AD7150
SCL SERIAL INTERFACE PROGRAMMING INTERFACE
CSENS1
- CDC EXC1 MUX CSENS2 CIN2 CAP DAC
DIGITAL FILTER
SDA OUT1
THRESHOLD DIGITAL OUTPUTS
EXCITATION EXC2
THRESHOLD
OUT2
GND
Figure 10. AD7150 Block Diagram
OVERVIEW
The AD7150 core is a high performance capacitance to digital converter (CDC), which allows the part to be interfaced directly to a capacitive sensor. The comparators compare the CDC result with thresholds, either fixed or dynamically adjusted by the on-chip adaptive threshold algorithm engine. Thus, the outputs indicate a defined change in the input sensor capacitance. The AD7150 also integrates an excitation source and CAPDAC for the capacitive inputs, an input multiplexer, a complete clock generator, a power down timer, control logic, and an I2Ccompatible serial interface for configuring the part and accessing the internal CDC data, status, etc., if required in the system. See Figure 10.
CSENS 0..4pF EXC EXCITATION
CAPACITANCE TO DIGITAL CONVERTER (CDC)
CLOCK GENERATOR 0x000 .. 0xFFF DATA CIN
-
MODULATOR
DIGITAL FILTER
Figure 11. CDC Simplified Block Diagram
CAPACITANCE TO DIGITAL CONVERTER
Figure 11 shows the CDC simplified functional diagram. The converter consists of a second order - (or charge balancing) modulator and a third order digital filter. The measured capacitance CX is connected between an excitation source and the - modulator input. The excitation signal is applied on the CX during the conversion and the modulator continuously samples the charge going through the CX. The digital filter processes the modulator output, which is a stream of 0s and 1s containing the information in 0 and 1 density. The data are processed by the adaptive threshold engine and output comparators; the data can be also read through the serial interface. The AD7150 is designed for floating capacitive sensors. Therefore, both CX plates have to be isolated from ground or any other fixed potential node in the system. The AD7150 features slew rate limiting on the excitation voltage output, which decrease the energy of higher harmonics on the excitation signal and dramatically improves the system EMC radiation performance.
CAPDAC
The AD7150 CDC core maximum full-scale input range is 4 pF. However, the part can accept a higher capacitance on the input and the offset (not-changing component) capacitance up to 10 pF can be balanced by a programmable on-chip CAPDAC.
CAPDAC 10pF CIN(+) CSENS 10..14pF EXC 0..4pF CDC
0x000 .. 0xFFF DATA
Figure 12. Using CAPDAC
The CAPDAC can be understood as a negative capacitance connected internally to the CIN pin. The CAPDAC has a 6-bit resolution and a monotonic transfer function. The example in Figure 12 shows how to use the CAPDAC to shift the CDC 4 pF input range to measure capacitance between 10 pF to 14 pF.
Rev. PrD | Page 8 of 24
Preliminary Technical Data
COMPARATOR AND THRESHOLD MODES
The AD7150 comparators and their thresholds can be programmed to operate in several different modes. In an adaptive mode, the threshold is dynamically adjusted and the comparator output will indicate fast changes and ignore slow changes in the input (sensor) capacitance Alternatively, the threshold can be programmed a constant (fixed) value and the output will indicate all changes in the input capacitance. The AD7150 logic output (active high) indicates either positive or negative change in the input capacitance, in both adaptive and fixed threshold modes; see Figure 13 and Figure 14.
POSITIVE CHANGE
AD7150
ADAPTIVE THRESHOLD
In an adaptive mode, the threshold(s) are dynamically adjusted, ensuring indication of fast changes (for example an object moving close to a capacitive proximity sensor) and eliminating slow changes in the sensor capacitance (usually caused by environment changes - e.g. humidity or temperature - or changes in the sensor dielectric material over time.). See Figure 17.
FAST CHANGE SLOW CHANGE
INPUT CAP. THRESHOLD
OUTPUT ACTIVE
POSITIVE THRESHOLD INPUT CAP. OUTPUT ACTIVE
OUTPUT TIME
Figure 17. Adaptive Threshold Indicates fast changes and eliminates slow changes in input capacitance
TIME
OUTPUT
Figure 13. Positive Threshold Mode Indicates positive change in input capacitance
NEGATIVE CHANGE
DATA AVERAGE
The adaptive threshold algorithm is based on an average calculated from previous CDC output data. The response of the average to an input capacitance step change (more exactly, response to the change in the CDC output data) is an exponential settling curve, which can be characterized by equation:
INPUT CAP. NEGATIVE THRESHOLD OUTPUT ACTIVE
OUTPUT TIME
Average( N ) = Average(0) + Change(1 - e N / TimeConst )
Where Average(N) is the value of average N complete CDC conversion cycles after a step change on the input, Average(0) is the value before the step change, and the TimeConstant can be selected in range between 2 and 65536 in steps of power of 2 by programming the ThrSettling bits in the setup registers. See Figure 18. See Register Descriptions.
INPUT CAPACITANCE (CDC DATA) CHANGE
Figure 14. Negative Threshold Mode Indicates negative change in input capacitance
Additionally, for the adaptive mode only, the comparators can work as "window" comparators, indicating input either inside or outside selected sensitivity band; see Figure 15 and Figure 16.
POSITIVE THRESHOLD INPUT CAP. NEGATIVE THRESHOLD OUTPUT ACTIVE INPUT INSIDE THRESHOLD WINDOW
DATA AVERAGE RESPONSE TIME
Figure 18 .Data Average Response to Data Step Change
OUTPUT TIME
Figure 15. In-Window (Adaptive) Threshold Mode
POSITIVE THRESHOLD INPUT CAP. NEGATIVE THRESHOLD
INPUT OUTSIDE THRESHOLD WINDOW
OUTPUT ACTIVE
OUTPUT TIME
Figure 16. Out-Window (Adaptive) Threshold Mode
Rev. PrD| Page 9 of 24
AD7150
SENSITIVITY
In adaptive threshold mode, the output comparator threshold is set as a defined distance ("sensitivity") above the data average, below the data average, or both, depending on the selected threshold mode of operation - see Figure 19. The sensitivity value is programmable in range of 0 to 255 LSBs of the 12-bit CDC converter. See Register Descriptions.
DATA
DATA AVERAGE + SENSITIVITY DATA AVERAGE DATA AVERAGE - SENSITIVITY
Preliminary Technical Data
LARGE CHANGE IN DATA
TIMEOUT
TIME
Figure 21. Threshold Timeout after a Large Change in CDC Data
POSITIVE THRESHOLD SENSITIVITY DATA AVERAGE SENSITIVITY NEGATIVE THRESHOLD OUTPUT ACTIVE
OUTPUT ACTIVE INPUT CAP. THRESHOLD LARGE CHANGE
TIMEOUT APPROACHING
TIME
OUTPUT TIME
Figure 19. Threshold Sensitivity
HYSTERESIS
In adaptive threshold mode, the comparator features hysteresis. The hysteresis is fixed to 1/4 of the threshold sensitivity and can be programmable ON or OFF. The comparator does not have any hysteresis in the fixed threshold mode.
DATA POSITIVE THRESHOLD
Figure 22. Approaching Timeout in Negative Threshold Mode Shortens False Output Trigger
LARGE CHANGE
TIMEOUT RECEDING
INPUT CAP. THRESHOLD
HYSTERSIS
OUTPUT
OUTPUT ACTIVE
TIME
DATA AVERAGE OUTPUT ACTIVE OUTPUT TIME
Figure 23. Positive Timeout in Negative Threshold Mode Shortens Period of Missing Output Trigger
AUTO CAPDAC ADJUSTMENT
In adaptive threshold mode, the part can dynamically adjust the CAPDAC to keep the CDC in an optimal operating capacitive range. When the AutoDAC function is enabled, the CAPDAC value is automatically incremented when the data average exceeds 3/4 of the CDC full range, and the CAPDAC value is decremented when the data average goes below 1/4 or the CDC full range. The AutoDAC increment or decrement step depends on the selected CDC capacitive input range. See Register Descriptions.
Figure 20. Threshold Hysteresis
TIMEOUT
In case of a large long change in the capacitive input, when the data average adapting to a new condition might take too long, a timeout can be set. The timeout becomes active (counting) when the CDC data goes outside the band of data average sensitivity. When the timeout elapses (a defined number of CDC conversions is counted), the data average, and thus the thresholds, are forced to follow the new CDC data value immediately. See Figure 21. The timeout can be set independently for "approaching" - for change in data towards the threshold, and for "receding" - for change in data away from the threshold. See Figure 22 and Figure 23. See Register Descriptions.
POWER DOWN TIMER
In power sensitive applications, the AD7150 can be set to automatically enter power down mode after a programmed period of time, in which the outputs have not been activated. The AD7150 can be then returned to a normal operational mode either via the serial interface or by power supply off - on sequence.
Rev. PrD | Page 10 of 24
Preliminary Technical Data
REGISTER DESCRIPTIONS
Table 5. Register Summary
Pointer Register Status Ch1 Data H Ch1 Data L Ch2 Data H Ch2 Data L Ch1 Average H Ch1 Average L Ch2 Average H Ch2 Average L Ch1 Sens / Thr H Ch1Tout / Thr L Ch1 Setup Ch2 Sens / Thr H Ch2 Tout / Thr L Ch2 Setup Configuration Power Down Timer Ch1 CAPDAC Ch2 CAPDAC Serial Number 3 Serial Number 2 Serial Number 1 Serial Number 0 Chip ID (Dec) (Hex) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 Dir R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R RngH2 0 ThrFixed 0 - 0 DacEn1 0 DacEn2 0 RngH1 0 PwrDown DacStep2 0 1 OUT2 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 C1/C2 0 Bit 1 RDY2 1
AD7150
Bit 0 RDY1 1
Default Value OUT1 DacStep1 1 0
Channel 1 Data - high byte, 0x00 Channel 1 Data - low byte, 0x00 Channel 2 Data - high byte, 0x00 Channel 2 Data - low byte, 0x00 Channel 1 Average - high byte, 0x00 Channel 1 Average - low byte, 0x00 Channel 2 Average - high byte, 0x00 Channel 2 Average - low byte, 0x00 Channel 1 Sensitivity (adaptive) / Threshold - high byte (fixed), 0x08 Channel 1 Timeout (adaptive) / Threshold - low byte (fixed), 0x86 RngL1 0 0 Hyst1 0 ThrSettling1 - 4-Bit Value 0x0B
Channel 2 Sensitivity (adaptive) / Threshold (fixed) - high byte, 0x08 Channel 2 Timeout (adaptive) / Threshold (fixed) - low byte, 0x86 RngL2 0 ThrMD1 0 - 0 DacAuto1 0 DacAuto2 0 0 ThrMD0 0 Hyst2 ThrSettling2 - 4-Bit Value MD0 1
0 0x0B EnCh1 EnCh2 MD2 MD1 1 1 0 0 Power Down Timeout - 6-Bit Value 0x00 Channel 1 CAPDAC - 6-Bit Value 0x00 Channel 2 CAPDAC - 6-Bit Value 0x00
Serial Number - byte 3 (MSB) Serial Number - byte 2 Serial Number - byte 1 Serial Number - byte 0 (LSB) Chip Identification Code
Rev. PrD| Page 11 of 24
AD7150
STATUS REGISTER
Address Pointer 0x00 8 Bits, Read Only, Default Value 0x53
This register indicates the status of the part. The register can be read via the 2-wire serial interface to query status of the outputs, check the CDC finished conversion and whether the CAPDAC has been changed by the auto CAPDAC function. Table 6. Status Register Bit Map
Bit Mnemonic Default Bit 7 PwrDown 0 Bit 6 DacStep2 1 Bit 5 OUT2 0 Bit 4 DacStep1 1 Bit 3 OUT1 0
Preliminary Technical Data
Bit 2 C1/C2 0
Bit 1 RDY2 1
Bit 0 RDY1 1
Table 7.
Bit 7 6 5 4 3 2 1 0 Mnemonic PwrDown DacStep2 OUT2 DacStep1 OUT1 C1/C2 RDY2 RDY1 Description PwrDown = 1 indicates that the part is in a power down mode. DacStep2 = 0 indicates that the CAPDAC Ch2 was changed after the last CDC conversion as part of the AutoDac function The bit value is updated after each finished CDC conversion on this channel. OUT2 = 1 indicates that the Ch2 data (CIN2 capacitance) crossed the threshold, according to the selected comparator mode of operation. The bit value is updated after each finished CDC conversion on this channel. DacStep1 = 0 indicates that the CAPDAC Ch2 was changed during the last conversion as part of the AutoDac function The bit value is updated after each finished CDC conversion on this channel. OUT1 = 1 indicates that the Ch1 data (CIN1 capacitance) crossed the threshold, according to the selected comparator mode of operation. The bit value is updated after each finished CDC conversion on this channel. The C1/C2 = 0 indicates the last finished CDC conversion was on channel 1, The C1/C2 = 1 indicates the last finished CDC conversion was on channel 2 RDY2 = 0 indicates finished CDC conversion on Ch2. The bit is reset back to 1 when the Ch2 data register is read via serial interface or after the part reset or power-up. RDY1= 0 indicates finished CDC conversion on Ch1. The bit is reset back to 1 when the Ch1 data register is read via serial interface or after the part reset or power-up.
DATA REGISTERS
Ch1 Address Pointer 0x01, 0x02 Ch2 Address Pointer 0x03,0x04 16 Bits, Read-Only, Default Value 0x0000
CDC output data. The AD7150 has a 12-bit converter, the 12bit result is mapped to the 12 MSB (most significant bits) of the 16-bit data register and the 4 LSB (least significant bits) are always 0. The register is updated after a finished conversion on the capacitive channel, with one exception: When the serial interface read operation from the data register is in progress, the data register is not updated and the new capacitance conversion result is lost. The stop condition on the serial interface is considered to be the end of the read operation. Therefore, to prevent incorrect data reading through the serial interface, the two bytes of the data register should be read sequentially using the register address pointer auto-increment feature of the serial interface.
AVERAGE REGISTERS
Ch1 Address Pointer 0x05, 0x06 Ch2 Address Pointer 0x07,0x08 16 Bits, Read-Only, Default Value 0x0000
Average calculated from the previous CDC data. The 12-bit CDC result corresponds to the 12 MSB of the average register. The settling time of the average can be set by programming the ThrSettling bits in the setup register. The average register is overwritten directly with the CDC output data, i.e., the history is forgotten, if the timeout is enabled and elapses.
FIXED THRESHOLD REGISTERS
Ch1 Address Pointer 0x09, 0x0A Ch2 Address Pointer 0x0C,0x0D 16 Bits, Read/Write, Factory Preset 0x0886
Set a constant threshold for the output comparator in the fixed threshold mode. The 12-bit CDC result corresponds to the 12 MSB of the threshold register. The threshold registers are not accessible in the adaptive threshold mode.
Rev. PrD | Page 12 of 24
Preliminary Technical Data
SENSITIVITY REGISTERS
Ch1 Address Pointer 0x09 Ch2 Address Pointer 0x0C 8 Bits, Read/Write, Factory Preset 0x08
Sensitivity register sets the distance of the positive threshold above the data average, and the distance of the negative threshold below the data average, in the adaptive threshold mode.
DATA
AD7150
The receding timeout starts when the CDC data cross the data averagesensitivity band in direction away from the threshold, according to the selected positive or negative threshold mode. The receding timeout is not used in the window threshold modes. The receding timeout elapses after 2TimeOutRec conversion cycles. When either approaching or receding timeout elapses (i.e., after the defined number of CDC conversions is counted), the data average, and thus the thresholds, are forced to follow the new CDC data value immediately. Timeout register = 0 disables both timeouts
DATA AVERAGE + SENSITIVITY LARGE CHANGE IN DATA TOWARDS THRESHOLD
POSITIVE THRESHOLD SENSITIVITY DATA AVERAGE SENSITIVITY NEGATIVE THRESHOLD OUTPUT ACTIVE
DATA AVERAGE THRESHOLD TIME
Figure 24. Threshold Sensitivity
The sensitivity is an 8-bit value and is mapped to the lower 8 bits of the 12-bit CDC data, i.e., corresponds to the 16-bit data register as shown in Figure 39.
SENSITIVITY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DATA H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DATA L Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TIMEOUT APPROACHING
TIME
Figure 26. Threshold Timeout Approaching after a Large Change in CDC Data towards Threshold
TIMEOUT RECEDING
DATA AVERAGE + SENSITIVITY
12-BIT CDC RESULT
DATA AVERAGE THRESHOLD LARGE CHANGE IN DATA AWAY FROM THRESHOLD TIME
Figure 25. Threshold Timeout after a Large Negative Change in CDC Data
TIMEOUT REGISTERS
Ch1 Address Pointer 0x0A Ch2 Address Pointer 0x0D 8 Bits, Read/Write, Factory Preset 0x86
Table 8. Timeout Register Bit Map
Bit Mnemonic Default Bit 7-4 TimeOutApr 0x08 Bit 3-0 TimeOutRec 0x06
Figure 27. Threshold Timeout Receding after a Large Change in CDC Data away from Threshold
The registers set timeouts for the adaptive threshold mode. The approaching timeout starts when the CDC data cross the data averagesensitivity band in direction towards the threshold, according to the selected positive, negative or window threshold mode. The approaching timeout elapses after 2TimeOutApr conversion cycles.
Rev. PrD| Page 13 of 24
AD7150
SETUP REGISTERS
Ch1 Address Pointer 0x0B Ch2 Address Pointer 0x0E 8 Bits, Read/Write, Factory Preset 0x0B
Table 9. Setup Register Bit Map
Bit Mnemonic Default Bit 7 RngH 0 Bit 6 RngL 0 Bit 5 0 Bit 4 Hyst 0 Bit 3
Preliminary Technical Data
Bit 2 0x0B
Bit 1
Bit 0
ThrSettling1 - 4-Bit Value
Table 10.
Bit 7 6 Mnemonic RngH RngL Description Range bits set the CDC input range. Also determine step for AutoDAC function RngH 0 0 1 1 5 4 3 2 1 0 Hyst ThrSettling RngL 0 1 0 1 Cin Range (pF) 2 0.5 1 4 AutoDAC Step (CAPDAC LSB) 4 1 2 8
This bit must be 0 for proper operation. Hyst = 1 disables hysteresis in adaptive threshold mode. Bit has no effect in fixed threshold mode - hysteresis is always disabled in the fixed threshold mode.
Determines the settling time constant of the data average, and thus the settling time of the adaptive thresholds. The response of the average to an input capacitance step change (more exact, response to the change in the CDC output data) is an exponential settling curve, characterized by equation:
Average( N ) = Average(0) + Change(1 - e N / TimeConst )
Where Average(N) is the value of average after N complete CDC conversion cycles after a step change on the input, Average(0) is the value before the step change, and the TimeConstant can be selected in range between 2 and 65536 conversion cycle multiples, in steps of power of 2, by programming the ThrSettling bits:
TimeConst = 2 ( ThrSettling +1)
INPUT CAPACITANCE (CDC DATA) CHANGE
DATA AVERAGE RESPONSE TIME
Figure 28 .Data Average Response to Data Step Change
Rev. PrD | Page 14 of 24
Preliminary Technical Data
CONFIGURATION REGISTER
Address Pointer 0x0F 8 Bits, Read/Write, Factory Preset 0x19
Table 11. Configuration Register Bit Map
Bit Mnemonic Default Bit 7 ThrFixed 0 Bit 6 ThrMD1 0 Bit 5 ThrMD0 0 Bit 4 EnCh1 1 Bit 3 EnCh2 1 Bit 2 MD2 0 Bit 1 MD1 0
AD7150
Bit 0 MD0 1
Table 12.
Bit 7 Mnemonic ThrFixed Description ThrFixed = 1 sets the fixed threshold mode. The outputs reflect comparison of data and a fixed (constant) value of the threshold registers. ThrFixed = 0 sets the adaptive threshold mode. The outputs reflect comparison of data to the adaptive thresholds, which is set dynamically based on the previous data and according to the other settings. These bits set the output comparators mode. OUTPUT ACTIVE WHEN ThrMD1 0 0 1 ThrMD0 0 1 0 Threshold Mode Negative Positive In-Window Adaptive Threshold Mode data < average - sensitivity data > average + sensitivity data > average - sensitivity AND data < average + sensitivity data < average - sensitivity OR data > average + sensitivity Fixed Threshold Mode Data < Threshold Data > Threshold -
6 5
ThrMD1 ThrMD0
1
1
Out-Window
-
4 3 2 1 0
EnCh1 EnCh2 MD2 MD1 MD0
Enables conversion on channel 1 Enables conversion on channel 2 Converter mode of operation setup. MD2 0 0 MD1 0 0 MD0 0 1 Mode Idle Cont. conversion Description Part is fully powered up, but performing no conversion Part is repeatedly performing conversions on the enabled channel(s). If two channels are enabled, part is sequentially switching between them. Part performs a single conversion on the enabled channel. If two channels are enabled, the part will perform two conversions, one on each channel. After finishing the conversion(s), the part goes to the idle mode. Powers down the on-chip circuits, except the digital interface. Do not use these modes.
0
1
0
Single conversion
0 1
1 X
1 X
Power-Down Reserved
Rev. PrD| Page 15 of 24
AD7150
POWER DOWN TIMER REGISTER
Address Pointer 0x10 8 Bits, Read/Write, Factory Preset 0x00
Table 13. Setup Register Bit Map
Bit Mnemonic Default Bit 7 - 0 Bit 6 - 0 Bit 5 Bit 4
Preliminary Technical Data
Bit 3 Bit 2 Bit 1 Power Down Timeout - 6-Bit Value 0xPP
Bit 0
Table 14.
Bit 7-6 5-0 Mnemonic Power Down Timeout Description These bits must be 0 for proper operation Defines period duration of the power down timeout. If the output comparator outputs have not been activated during the programmed period, the part enters automatically power down mode. The part can be then returned to a normal operational mode either via the serial interface or by power supply off - on sequence. The period is programmable in steps of 4 hours. For example, setting value to 0x06 sets the duration to 24 hours, the maximum value of 0x3F corresponds to approximately 10.5 days. Value of 0x00 disables the power down timeout and the part will not enter power down mode automatically.
CAP DAC B REGISTERS
Ch1 Address Pointer 0x11 Ch2 Address Pointer 0x12 8 Bits, Read/Write, Factory Preset 0x00
Table 15. Setup Register Bit Map
Bit Mnemonic Default Bit 7 DacEn P Bit 6 DacAuto1 P Bit 5 Bit 4 Bit 3 0xPP Bit 2 Bit 1 Bit 0 Channel 1 CAPDAC - 6-Bit Value
Table 16.
Bit 7 6 Mnemonic DacEn DacAuto Description DacEn = 1 enables capacitive DAC DacAuto = 1 enables the AutoDAC function in the adaptive threshold mode. When the AutoDAC function is enabled, the part dynamically adjust the CAPDAC to keep the CDC in an optimal operating capacitive range. The CAPDAC value is automatically incremented when the data average exceeds 3/4 of the CDC full range, and the CAPDAC value is decremented when the data average goes below 1/4 or the CDC full range. The AutoDAC increment or decrement step depends on the selected CDC capacitive input range. Bit has no effect in fixed threshold mode - AutoDAC function is always disabled in the fixed threshold mode. CAPDAC value, Code 0x00 0 pF, Code 0x3F CAPDAC full range.
5-0
CAPDAC
SERIAL NUMBER REGISTERS
Address Pointer 0x13, 0x14, 0x15, 0x16 32 Bits, Read Only, 0xXXXX
Register holds a serial number, unique for each individual part.
CHIP ID REGISTERS
Address Pointer 0x17 8 Bits, Read Only, 0xXX
Chip identification code, used in factory manufacturing and test.
Rev. PrD | Page 16 of 24
Preliminary Technical Data
SERIAL INTERFACE
The AD7150 supports an I2C-compatible 2-wire serial interface. The two wires on the I2C bus are called SCL (clock) and SDA (data). These two wires carry all addressing, control, and data information one bit at a time over the bus to all connected peripheral devices. The SDA wire carries the data, while the SCL wire synchronizes the sender and receiver during the data transfer. I2C devices are classified as either master or slave devices. A device that initiates a data transfer message is called a master, while a device that responds to this message is called a slave. To control the AD7150 device on the bus, the following protocol must be followed. First, the master initiates a data transfer by establishing a start condition, defined by a high-tolow transition on SDA while SCL remains high. This indicates that the start byte follows. This 8-bit start byte is made up of a 7-bit address plus an R/W bit indicator. All peripherals connected to the bus respond to the start condition and shift in the next 8 bits (7-bit address + R/W bit). The bits arrive MSB first. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as the acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. An exception to this is the general call address, which is described later in this document. The idle condition is where the device monitors the SDA and SCL lines waiting for the start condition and the correct address byte. The R/W bit determines the direction of the data transfer. A Logic 0 LSB in the start byte means that the master writes information to the addressed peripheral. In this case the AD7150 becomes a slave receiver. A Logic 1 LSB in the start byte means that the master reads information from the addressed peripheral. In this case, the AD7150 becomes a slave transmitter. In all instances, the AD7150 acts as a standard slave device on the I2C bus. The start byte address for the AD7150 is 0x90 for a write and 0x91 for a read.
AD7150
incrementer allow block data to be written or read from the starting address and subsequent incremental addresses. In continuous conversion mode, the address pointers' autoincrementer should be used for reading a conversion result. That means, the three data bytes should be read using one multibyte read transaction rather than three separate single byte transactions. The single byte data read transaction may result in the data bytes from two different results being mixed. The same applies for six data bytes if both the capacitive and the voltage/temperature channel are enabled. The user can also access any unique register (address) on a oneto-one basis without having to update all the registers. The address pointer register contents cannot be read. If an incorrect address pointer location is accessed or, if the user allows the auto-incrementer to exceed the required register address, the following applies: * In read mode, the AD7150 continues to output various internal register contents until the master device issues a no acknowledge, start, or stop condition. The address pointers' auto-incrementer's contents are reset to point to the status register at address 0x00 when a stop condition is received at the end of a read operation. This allows the status register to be read (polled) continually without having to constantly write to the address pointer. In write mode, the data for the invalid address is not loaded into the AD7150 registers but an acknowledge is issued by the AD7150.
*
WRITE OPERATION
When a write is selected, the byte following the start byte is always the register address pointer (subaddress) byte, which points to one of the internal registers on the AD7150. The address pointer byte is automatically loaded into the address pointer register and acknowledged by the AD7150. After the address pointer byte acknowledge, a stop condition, a repeated start condition, or another data byte can follow from the master. A stop condition is defined by a low-to-high transition on SDA while SCL remains high. If a stop condition is ever encountered by the AD7150, it returns to its idle condition and the address pointer is reset to address 0x00. If a data byte is transmitted after the register address pointer byte, the AD7150 load this byte into the register that is currently addressed by the address pointer register, send an acknowledge, and the address pointer auto-incrementer automatically increments the address pointer register to the next internal register address. Thus, subsequent transmitted data bytes are loaded into sequentially incremented addresses.
READ OPERATION
When a read is selected in the start byte, the register that is currently addressed by the address pointer is transmitted on to the SDA line by the AD7150. This is then clocked out by the master device and the AD7150 awaits an acknowledge from the master. If an acknowledge is received from the master, the address autoincrementer automatically increments the address pointer register and outputs the next addressed register content on to the SDA line for transmission to the master. If no acknowledge is received, the AD7150 return to the idle state and the address pointer is not incremented. The address pointers' auto-
Rev. PrD| Page 17 of 24
AD7150
If a repeated start condition is encountered after the address pointer byte, all peripherals connected to the bus respond exactly as outlined above for a start condition, that is, a repeated start condition is treated the same as a start condition. When a master device issues a stop condition, it relinquishes control of the bus, allowing another master device to take control of the bus. Hence, a master wanting to retain control of the bus issues successive start conditions known as repeated start conditions.
Preliminary Technical Data
GENERAL CALL
When a master issues a slave address consisting of seven 0s with the eighth bit (R/W bit) set to 0, this is known as the general call address. The general call address is for addressing every device connected to the I2C bus. The AD7150 acknowledge this address and read in the following data byte. If the second byte is 0x06, the AD7150 are reset, completely uploading all default values. The AD7150 do not respond to the I2C bus commands (do not acknowledge) during the default values upload for approximately TBD s. The AD7150 do not acknowledge any other general call commands.
AD7150 RESET
To reset the AD7150 without having to reset the entire I2C bus, an explicit reset command is provided. This uses a particular address pointer word as a command word to reset the part and upload all default settings. The AD7150 do not respond to the I2C bus commands (do not acknowledge) during the default values upload for approximately TBD s. The reset command address word is 0xBF.
SDATA
SCLOCK
S
1-7
8
9
1-7
8
9
1-7 DATA
8
9 ACK
P STOP
START ADDR R/W ACK SUBADDRESS ACK
Figure 29. Bus Data Transfer
WRITE SEQUENCE
S
SLAVE ADDR A(S) LSB = 0
SUB ADDR
A(S)
DATA
A(S) LSB = 1
DATA
A(S) P
S = START BIT P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 30. Write and Read Sequences
Rev. PrD | Page 18 of 24
05468-007
READ SEQUENCE
05468-006
S
SLAVE ADDR A(S)
SUB ADDR
A(S) S
SLAVE ADDR
A(S)
DATA
A(M)
DATA
A(M) P
Preliminary Technical Data
HARDWARE DESIGN CONSIDERATIONS
OVERVIEW
The AD7150 is an interface to capacitive sensors. On the input side, the sensor (CX) can be connected directly between the AD7150 EXC and the CIN pins. The way how is it connected and the electrical parameters of the sensor connection, such as parasitic resistance or capacitance, can affect the system performance. Therefore, any circuit with additional components in the capacitive front end, such as overvoltage protection, has to be carefully designed considering the AD7150 specified limits and information provided in this section. On the output side, the AD7150 can work as a standalone device, using the power-up default register settings and flagging the result on digital outputs. Alternatively, the AD7150 can be interfaced to a microcontroller via the 2-wire serial interface, offering flexibility by overwriting the AD7150 register values from the host with a user specific setup.
AD7150
PARASITIC RESISTANCE TO GROUND
RGND1
CIN
CDC
DATA
CX
EXC
Figure 32. Parasitic Resistance to Ground
The AD7150 CDC result would be affected by a leakage current from the CX to ground, therefore the CX should be isolated from the ground. (The equivalent resistance between the CX and ground should be maximized - see Figure 32). The limit will be specified after the AD7150 characterization.
PARASITIC CAPACITANCE TO GROUND
PARASITIC PARALLEL RESISTANCE
CGND1
CIN
CDC
DATA
CIN
CDC
DATA
CX
CX
RP
EXC
Figure 31. Parasitic Capacitance to Ground
The CDC architecture used in the AD7150 measures the capacitance CX connected between the EXC pin and the CIN pin. In theory, any capacitance CGND to ground should not affect the CDC result (see Figure 31). The practical implementation of the circuitry in the chip implies certain limits and the result is gradually affected by capacitance to ground. See the allowed capacitance to GND in the specification table for CIN and excitation. Further details will be specified after the AD7150 characterization.
Figure 33. Parasitic Parallel Resistance
The AD7150 CDC measures the charge transfer between EXC pin and CIN pin. Any resistance connected in parallel to the measured capacitance CX (see Figure 33), such as the parasitic resistance of the sensor, also transfers charge. Therefore, the parallel resistor is seen as an additional capacitance in the output data. The equivalent parallel capacitance (or error caused by the parallel resistance) can be approximately calculated as
CP =
1 RP x FEXC x 4
Where RP is the parallel resistance and FEXC is the excitation frequency. Further details will be specified after the AD7150 characterization.
Rev. PrD | Page 19 of 24
05468-022
EXC
05468-012
CGND2
05468-013
RGND2
AD7150
PARASITIC SERIAL RESISTANCE
Preliminary Technical Data
INPUT EMC PROTECTION
39k 82k CIN
CX
68pF
22pF
CDC
EXC
RS1
CIN
CDC
DATA
10k
47pF
GND
CX
Figure 36. AD7150 CIN EMC Protection
EXC
05468-023
RS2
Figure 34. Parasitic Serial Resistance
Some applications may have specific requirements for EMC protection. Figure 36 shows one of the possible input circuit configurations improving the system EMC robustness.
The AD7150 CDC result is affected by a resistance in series with the measured capacitance. The total serial resistance, which refers to RS1 + RS2 on Figure 34, should be in order of hundreds . Further details will be specified after the AD7150 characterization.
INPUT OVERVOLTAGE PROTECTION
CDC
RS1 CX RS2 CIN
EXC2
GND
Figure 35. AD7150 CIN Overvoltage Protection
The AD7150 capacitive input has an internal ESD protection. However, some applications may require an additional overvoltage protection depending on the application specific requirements. Any additional circuit in the capacitive front end has to be carefully designed, especially with respect to the limits recommended for max. capacitance to ground, max. serial resistance, max. leakage, etc. Further details will be specified after the AD7150 characterization.
Rev. PrD | Page 20 of 24
Preliminary Technical Data
APPLICATION EXAMPLES
VDD CIN1 SDA
AD7150
AD7150
CSENS1 EXC1 CIN2
SCL OUT1
LED1
LED2 3.6V BATTERY
CSENS2
EXC2
OUT2
GND
Figure 37. AD7150 Standalone Operation Application Diagram
+3.3V VDD CIN1 SDA
SDA SCL
AD7150
CSENS1 EXC1 CIN2
SCL
HOST uC
OUT1 CSENS2 EXC2 OUT2
IRQ1 IRQ2
GND
Figure 38. AD7150 Interfaced to a Host Microcontroller
Rev. PrD | Page 21 of 24
AD7150
Preliminary Technical Data
Notes
Rev. PrD | Page 22 of 24
Preliminary Technical Data
AD7150
Notes
Rev. PrD | Page 23 of 24
AD7150
Preliminary Technical Data
3.00 BSC
10
6
3.00 BSC
1 5
4.90 BSC
PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.00 0.27 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA 1.10 MAX 8 0 0.80 0.60 0.40
SEATING PLANE
0.23 0.08
Figure 39. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c) 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
PR06517-0-11/06(PrD)
Rev. PrD | Page 24 of 24

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